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ALTERA EPXA4F672I2 technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Свойство продукта | Значение свойства | |
|---|---|---|
| Классификация | Embedded - FPGAs (Field Programmable Gate Array) with Microcontrollers | |
| Марка | ALTERA | |
| Package / Case | 672-BBGA, FCBGA | |
| Mounting Type | Surface Mount | |
| Mount | Surface Mount | |
| Surface Mount | YES | |
| Number of Pins | 672Pins | |
| Supplier Device Package | 672-FBGA (27x27) | |
| Number of Terminals | 672Terminals | |
| RoHS | Compliant | |
| Package Description | BGA, | |
| Package Style | GRID ARRAY | |
| Moisture Sensitivity Levels | 3 | |
| Package Body Material | PLASTIC/EPOXY | |
| Supply Voltage-Nom | 1.8 V | |
| Reflow Temperature-Max (s) | 30 | |
| Supply Voltage-Min | 1.71 V | |
| Rohs Code | No | |
| Manufacturer Part Number | EPXA4F672I2 | |
| Package Code | BGA | |
| Package Shape | SQUARE | |
| Manufacturer | Intel Corporation | |
| Part Life Cycle Code | Obsolete | |
| Number of I/O Lines | 426I/O Lines | |
| Ihs Manufacturer | INTEL CORP | |
| Supply Voltage-Max | 1.89 V | |
| Risk Rank | 5.79 | |
| Packaging | Tray | |
| Series | Excalibur™ | |
| Operating Temperature | -40°C ~ 100°C | |
| JESD-609 Code | e0 | |
| Part Status | Obsolete |
| Свойство продукта | Значение свойства | |
|---|---|---|
| ECCN Code | 3A001.A.7.A | |
| Terminal Finish | TIN LEAD | |
| Max Operating Temperature | 100 °C | |
| Min Operating Temperature | -40 °C | |
| HTS Code | 8542.39.00.01 | |
| Voltage - Supply | 1.8V | |
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | 220 | |
| Terminal Pitch | 1 mm | |
| Reach Compliance Code | compliant | |
| Frequency | 200 MHz | |
| JESD-30 Code | S-PBGA-B672 | |
| Qualification Status | Not Qualified | |
| Operating Supply Voltage | 1.8 V | |
| Interface | EBI/EMI, UART/USART | |
| Speed | 200MHz | |
| Organization | 0 DEDICATED INPUTS, 426 I/O | |
| Seated Height-Max | 2.1 mm | |
| Programmable Logic Type | LOADABLE PLD | |
| Number of Logic Elements/Cells | 16640Logic Elements/Cells | |
| EEPROM Size | -- | |
| Number of Logic Blocks (LABs) | 16640Logic Blocks (LABs)s | |
| Output Function | MACROCELL | |
| Core Type | 32-Bit ARM9 | |
| Data SRAM Bytes | 64K | |
| FPGA Gates | 400K | |
| Program SRAM Bytes | 128K | |
| FPGA Core Cells | 16640 | |
| FPGA SRAM | -- | |
| Width | 27 mm | |
| Length | 27 mm |