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Altera Corporation EP1800GI-3 technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
Свойство продукта | Значение свойства | |
---|---|---|
Классификация | Embedded - PLDs (Programmable Logic Device) | |
Марка | ||
Surface Mount | NO | |
Number of Terminals | 68Terminals | |
Rohs Code | No | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | ALTERA CORP | |
Part Package Code | PGA | |
Package Description | WPGA, PGA68,11X11 | |
Clock Frequency-Max | 18.5 MHz | |
Moisture Sensitivity Levels | 1 | |
Number of I/O Lines | 48I/O Lines | |
Operating Temperature-Max | 85 °C | |
Operating Temperature-Min | -40 °C | |
Package Body Material | CERAMIC, METAL-SEALED COFIRED | |
Package Code | WPGA | |
Package Equivalence Code | PGA68,11X11 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY, WINDOW | |
Supply Voltage-Max | 5.5 V | |
Supply Voltage-Min | 4.5 V | |
Supply Voltage-Nom | 5 V | |
JESD-609 Code | e0 |
Свойство продукта | Значение свойства | |
---|---|---|
Terminal Finish | TIN LEAD | |
Additional Feature | 48 MACROCELLS | |
HTS Code | 8542.39.00.01 | |
Terminal Position | PERPENDICULAR | |
Terminal Form | PIN/PEG | |
Peak Reflow Temperature (Cel) | 220 | |
Terminal Pitch | 2.54 mm | |
Reach Compliance Code | compliant | |
Pin Count | 68 | |
JESD-30 Code | S-CPGA-P68 | |
Qualification Status | Not Qualified | |
Temperature Grade | INDUSTRIAL | |
Propagation Delay | 80 ns | |
Organization | 12 DEDICATED INPUTS, 48 I/O | |
Seated Height-Max | 5.0038 mm | |
Programmable Logic Type | UV PLD | |
Output Function | MACROCELL | |
Number of Macro Cells | 48Macro Cells | |
JTAG BST | NO | |
Number of Dedicated Inputs | 12Dedicated Inputs | |
In-System Programmable | NO | |
Length | 27.94 mm | |
Width | 27.94 mm |