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XCKU035-2FBVA676E Технические параметры
Xilinx Inc. XCKU035-2FBVA676E technical specifications, attributes, parameters and parts with similar specifications to Silicon Labs SI1084-A-GM.
| Свойство продукта | Значение свойства | |
|---|---|---|
| Классификация | Embedded - FPGAs (Field Programmable Gate Array) | |
| Марка | ||
| Factory Lead Time | 10 Weeks | |
| Contact Plating | Copper, Silver, Tin | |
| Mount | Surface Mount | |
| Mounting Type | Surface Mount | |
| Package / Case | 676-BBGA, FCBGA | |
| Number of Pins | 676Pins | |
| Number of I/Os | 312I/Os | |
| Operating Temperature | 0°C~100°C TJ | |
| Packaging | Bulk | |
| Series | Kintex® UltraScale™ | |
| Published | 2012 | |
| JESD-609 Code | e1 | |
| Part Status | Active | |
| Moisture Sensitivity Level (MSL) | 4 (72 Hours) | |
| Number of Terminations | 676Terminations | |
| ECCN Code | 3A991.D | |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) | |
| Packing Method | TRAY | |
| Voltage - Supply | 0.922V~0.979V |
| Свойство продукта | Значение свойства | |
|---|---|---|
| Terminal Position | BOTTOM | |
| Terminal Form | BALL | |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
| Supply Voltage | 0.95V | |
| Terminal Pitch | 1mm | |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
| Number of Outputs | 312Outputs | |
| Qualification Status | Not Qualified | |
| Operating Supply Voltage | 950mV | |
| Power Supplies | 0.95V | |
| RAM Size | 2.4MB | |
| Organization | 1700 CLBS | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Number of Logic Elements/Cells | 444343Logic Elements/Cells | |
| Total RAM Bits | 19456000 | |
| Number of LABs/CLBs | 25391LABs/CLBs | |
| Speed Grade | 2 | |
| Number of Registers | 406256Registers | |
| Number of CLBs | 1700CLBs | |
| RoHS Status | ROHS3 Compliant |
XCKU035-2FBVA676E Документы
- DatasheetsUltraScale? Architecture Product Overview Kintex? UltraScale? FPGA Datasheet Wireless Bluetooth? Low Energy Modules Overview
- Environmental InformationXilinx RoHS3
- PCN Design/SpecificationUltrascale & Virtex Dev Spec Chg 20/Dec/2016
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